Circuit Issues
Templates
#0040InterfaceDRC cleanv1.0

Level translator 3.3 V → 5 V, one channel

Single unidirectional buffer with TTL input thresholds that turns a 3.3 V logic signal into a clean 5 V signal, typically the data line of WS2812 / SK6812 LEDs driven by an ESP32. Series resistors on the input and the output. The output enable is set by a resistor option: always enabled (fitted by default) or disabled. The labels carry the block ID, so several instances can sit on one sheet.

3D render of the 0040 Level translator 3.3 V → 5 V, one channel KiCad design block
3D render (KiCad 10)
3D render of the 0040 Level translator 3.3 V → 5 V, one channel KiCad design block
3D render, top view (KiCad 10)
Schematic of the 0040 Level translator 3.3 V → 5 V, one channel KiCad design block
Schematic (KiCad 10)

Key specifications

  • Supply 4.5–5.5 V
  • One channel, unidirectional, up to about 100 MHz
  • TTL input threshold: 3.3 V logic drives it with margin
  • Output enable by resistor option (always on by default)

Design notes

  • One direction only (3.3 V → 5 V). For a bidirectional UART use 0165.

Seen in real hardware

Flossa AI Controller PCBA, 3D render, isometric view

Flossa AI Controller

Uses this block alongside 9 other templates · flossa.ai

Coming soon

This block is not available yet. It is released once its checks are complete. Planned price: €29.

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Planned package contents

  • KiCad 10 design block

    Schematic and PCB layout fragment; symbols and footprints embedded

  • BOM (CSV)

    Manufacturer part numbers and LCSC codes

  • Schematic PDF + README

    Interface, specs, population options and design notes

  • 3D models

    STEP models of the special parts; standard parts use KiCad’s 3D library

  • template.yaml

    Machine-readable interface and limits

PCB Composer

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About PCB Composer

Development status

Block ID0040
Block name0040-level-translator-3v3-to-5v
Version1.0
StatusDRC clean – Schematic and layout pass the KiCad rule checks; not yet verified on hardware.
Open review itemsNone
PCB layoutRule-checked layout fragment
FormatKiCad 10 design block (schematic + PCB)
Last change2026-11-03

Interface

Hierarchical labels the block exposes to the rest of your design. ${ID} is replaced per instance, so several copies can live on one sheet.

NetDirectionDescription
VDDPower in5 V supply of the buffer
TRANS_IN_${ID}Input3.3 V logic input, series resistor
TRANS_OUT_${ID}Output5 V logic output, series resistor

FAQ

Which KiCad version do I need?

KiCad 10. The files are saved in the KiCad 10 format and are meant to be placed with KiCad’s Design Blocks feature (schematic block, then “Apply Design Block Layout” on the PCB).

Do I need the Circuit Issues part library?

No. Symbols are embedded in the schematic and footprints in the PCB, so the block opens on its own. Parts carry manufacturer part numbers and LCSC codes.

Is the layout production-ready?

The layout fragment passes the KiCad design rule check. Route it into your board and run DRC with your own fab rules.

Can I use the template in a commercial product?

The licence terms are published together with the first release.

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Designed